OpenVMS Alpha Guide to Upgrading Privileged-Code Applications

The Image Registry facility has several benefits, particularly when you have only image files, not source or object files. In addition, it eases version compatibility problems on mixed-version clusters because the same images can be used on all nodes. It also simplifies the addition of third-party software and device drivers to the system.

The registry is a file that contains registered images. These images include main images (images that you can run directly), shared libraries, and device drivers that are identified by name, the image identification string, and the link time of the image. The registered images bypass normal system version checking in the INSTALL, system image loader, and image activator phases. With the Image Registry facility, images for different versions of applications can be registered independently.

Images linked as part of installation need not be registered because they match the version of the running system. However, linking during installation cannot ensure the absence of system version dependencies.

2.5.1 Version Identification (ID) Number Change to Three Subsystems

The OpenVMS executive defines 18 logical subsystems. Each of these subsystems contains its own version identification (ID) number. This modularization makes it possible for OpenVMS releases to include changes to a portion of the executive, impacting only those privileged programs which use that portion of the executive.

For OpenVMS ALpha Version 7.0, the following 3 subsystems have changed, and their version IDs have been incremented:

I/O
Memory Management
Process Scheduling

Developers should check privileged code (that is, any image linked against the system symbol table SYS$BASE_IMAGE.EXE) to determine whether the image is affected by the changes to the subsystems. If the code is affected, the developer should make any necessary changes.

Chapter 3
Replacements for Removed Privileged Symbols

This chapter describes the closest equivalent mechanism to a number of internal routines, data structure cells, and system data cells that have been removed in OpenVMS Alpha Version 7.0.

Each table lists the previous name, any replacements, and a brief explanation.

Important
The internal data structure fields, routines, macros, and data cells described in this chapter should not be interpreted as being part of the documented interfaces that drivers or other privileged software should routinely depend on.
If you were using the removed mechanism correctly, this chapter will assist you in using the closest equivalent in OpenVMS Alpha Version 7.0. However, you should not use this as an opportunity to start using these mechanisms. Doing so is likely to increase the work required to maintain compatibility of your privileged software with future releases of OpenVMS.

3.1 Removed Date Structure Fields

Table 3-1 lists the data structure fields that have been removed as of OpenVMS Alpha Version 7.0.

Table 3-1 Removed Date Structure Fields
Removed Field Replacement Comments

BOD$L_BASEPVA BOD$PQ_BASEPVA 64-bit process virtual address of buffer mapped by the buffer object. See Appendix A.

CDRP$L_AST cdrp$pq_acb64_ast Increased to a quadword and renamed.

CDRP$L_ASTPRM CDRP$Q_A See Appendix A.

CDRP$L_IOSB CDRP$PQ_IOSB See Appendix A.

CPT$L_IOVA CPT$PQ_IOVA Increased to a quadword and renamed.

DMP$M_BITS_12_15 Still have this field. Same value.

DMP$S_BITS_12_15 Still have this field. Same value.

DMP$V_BITS_12_15 Still have this field. Same value.

DYN$C_F64_F64DATA TBS---Dollar

DYN$C_NET_TIM_TEB DYN$C_NET_TIM_NTEB Renamed because the DECnet structure it indicates (network timer element block) was renamed from TEB to NTEB.

FDT_CONTEXT$L_QIO_R1_VALUE FDT_CONTEXT$Q_QIO_R1_VALUE See Appendix A.

IRP$L_AST IRP$PQ_ACB64_AST Removed to ensure that any reference to the $QIO astadr via a 32-bit address and astprm as a 32-bit value are detected at compile-time or link-time.

IRP$L_ASTPRM IRP$Q_ACB64_ASTPRM Removed to ensure that any reference to the $QIO astadr via a 32-bit address and astprm as a 32-bit value are detected at compile-time or link-time.

IRP$L_IOSB IRP$PQ_IOSB Removed to ensure that any reference to the $QIO iosb via a 32-bit address is detected at compile-time or link-time.

IRPE$L_BCNT1 IRPE$L_BCNT See Appendix A.

IRPE$L_BCNT2 None. Removed.

IRPE$L_BOFF1 IRPE$L_BOFF See Appendix A.

IRPE$L_BOFF2 None. Removed.

IRPE$L_SVAPTE1 IRPE$L_SVAPTE

IRPE$L_SVAPTE2 None. Removed.

LCKCTX$L_CPLADR LCKCTX$PQ_CPLADR Increased in length to quadword.

LCKCTX$L_CPLPRM LCKCTX$Q_CPLPRM Increased in length to quadword.

LCKCTX$L_CR3 LCKCTX$Q_CR3 Increased in length to quadword.

LCKCTX$L_CR4 LCKCTX$Q_CR4 Increased in length to quadword.

LCKCTX$L_CR5 LCKCTX$Q_CR5 Increased in length to quadword.

LCKCTX$L_CRETADR LCKCTX$PQ_CREADR Increased in length to quadword.

LCKCTX$L_CTX_PRM1 LCKCTX$Q_CTX_PRM1 Increased in length to quadword.

LCKCTX$L_CTX_PRM2 LCKCTX$Q_CTX_PRM2 Increased in length to quadword.

LCKCTX$L_CTX_PRM3 LCKCTX$Q_CTX_PRM3 Increased in length to quadword.

LCKCTX$L_RET1 LCKCTX$PQ_RET1 Increased in length to quadword.

LCKCTX$L_TMP1 LCKCTX$Q_TMP1 Increased in length to quadword.

LKB$C_ACBLEN Removed.

LKB$K_ACBLEN Removed.

LKB$L_AST LKB$PQ_AST Increased in length to quadword.

LKB$L_ASTPRM LKB$Q_ASTPRM Increased in length to quadword.

LKB$L_BLKASTADR LKB$PQ_CPLASTADR Increased in length to quadword.

LKB$L_CPLASTADR LKB$PQ_CPLASTADR Increased in length to quadword.

LKB$L_LKSB LKB$PQ_LKSB Increased in length to quadword.

LKB$L_OLDASTPRM LKB$Q_OLDASTPRM Increased in length to quadword.

LKB$L_OLDBLKAST LKB$PQ_OLDBLKAST Increased in length to quadword.

LMB$C_GBL No name change. Value changed from 2 to 3.

LMB$C_PROCESS No name change. Value changed from 3 to 4.

LMB$C_S0 LMB$C_S0S1 Value = 1

LMB$C_SPT LMB$C_SPTW Not guaranteed to be in a dump.

LMB$L_BAD_MEM_END LMB$PQ_BAD_MEM_END Supports a 64-bit address.

LMB$L_BAD_MEM_START LMB$PQ_BAD_MEM_START Supports a 64-bit address.

LMB$L_HOLE_START_VA LMB$PQ_BAD_MEM_START Supports a 64-bit address.

LMB$L_HOLE_TOTAL_PAGES LMB$Q_HOLE_TOTAL_PAGES Supports a 64-bit address.

MMG$C_PTSPACE_OFFSET
MMG$K_PTSPACE_OFFSET MMG$GL_L1_INDEX Compile-time constant that defined a fixed base address for page table address space. This has been replaced by a run-time mechanism which chooses a base address for page table address space during bootstrap, with the index of level 1 page table entry used to map the page tables stored in the new data cell.

PCB$L_ADB_LINK None Supported a feature that was never implemented.

PCB$L_PSX_ACTPRM PCB$Q_PSX_ACTPRM Increased in length to quadword.

PCB$L_TOTAL_EVTAST None Supported a feature that was never implemented.

PFN$C_ENTRY_SHIFT_SIZE None The size of a single PFN database entry was formerly a power of two. As of Version 7.0, that is no longer true and the symbol was deleted.

PFN$L_PTE This offset in the PFN database was replaced with a new PTE backpointer mechanism that is capable of supporting page table entries that reside in 64-bit virtual address space. Any code that formerly touched PFN$L_PTE must be recoded to use one of the following macros supplied in LIB.MLB:

ACCESS_BACKPOINTER
ESTABLISH_BACKPOINTER
TEST_BACKPOINTER

ACCESS_BACKPOINTER Accepts a PFN database entry address and returns a virtual address at which you may access the PTE that maps that PFN. This replaces a fetch of a SVAPTE from PFN$L_PTE, which would subsequently be used as an operand for a memory read or write instruction.

ESTABLISH_BACKPOINTER Replaces a write of a SVAPTE to PFN$L_PTE.

TEST_BACKPOINTER Replaces a test for zero in PFN$L_PTE.

PFN$L_REFCNT INCREF
DECREF This offset in the PFN database was replaced with a differently sized offset that is packed together with other fields in the PFN database. The supplied macro INCREF should be used to replace any existing increment of the value in PFN$L_REFCNT, while DECREF should be used to replace any existing decrement.

PFN$L_WSLX PFN$L_WSLX_QW This offset was renamed to reflect a fundamental change in working set list indexes. Prior to Version 7.0, the working set list index (WSLX) was a longword index. The WSLX has become a quadword index as of Version 7.0, therefore the name of the offset was changed to focus attention on existing code that must be changed to view the value stored at this offset as a quadword index rather than as a longword index.

PHD$C_PHDPAGCTX None Supported a feature that was never implemented.

PHD$L_BAK PHD$L_BAK_ARRAY PHD$L_BAK contained an offset to an internally maintained array which was used to support swapping of the balance slot contents. As of Version 7.0, the implementation of this array changed to better accommodate the balance slot contents. PHD$L_BAK was replaced by PHD$L_BAK_ARRRAY which is the symbolic offset from the start of the process header to where this array begins.

PHD$L_L2PT_VA L2PTE_VA This process header offset formerly contained the system space address of the process's level 2 page table page that was used to map P0 and P1 spaces. As of Version 7.0, the page tables no longer reside in the balance slot, and a process is no longer limited to having only one level 2 page table page. This offset was used to derive addresses of level 2 page table entries. Use the L2PTE_VA macro to derive from a given VA the address of the level 2 PTE that maps that VA.

PHD$L_L3PT_VA
PHD$L_L3PT_VA_P1 PTE_VA These process header offsets formerly contained the system space addresses of the bases of the P0 and P1 page tables that resided in the process's balance slot. As of Version 7.0, the page tables no longer reside in the balance slot, and the conceptual overlap of the P0 and P1 page tables in virtual memory no longer exists. Use the PTE_VA macro to derive from a given VA the address of the level 3 PTE that maps that VA.

PHD$L_P0LENGTH None Different page table layout.

PHD$L_P1LENGTH None Different page table layout.

PHD$L_PSTBASMAX PHD$L_PST_BASE_MAX Contains new-style section index.

PHD$L_PSTBASOFF PHD$L_PST_BASE_OFFSET Name changed.

PHD$L_PSTFREE PHD$L_PST_FREE Contains new-style section index.

PHD$L_PSTLAST PHD$L_PST_LAST Contains new-style section index.

PHD$L_PTWSLELCK
PHD$L_PTWSLEVAL PFN database These process header offsets formerly contained internal bookkeeping information for managing page table pages for a process. These have been replaced by a bookkeeping mechanism that resides in the PFN database entries for page table pages. It is highly unlikely that anyone is affected by this change.

PHD$L_QUANT KTB$L_QUANT

PHD$L_WSL CTL$GQ_WSL You can no longer count on WSL (data cell) following PHD, use pointer to WSL in CTL$GQ_WSL instead.

PHD$L_WSLX None WSLX array is no longer in PHD as a result of the new swapper design.

PTE$L_COUNT PTE$L_FREE_COUNT Offset to the number of free PTEs in a free PTE structure.

PTE$L_LINK PTE$Q_INDEX Contains an index to the next free element in the free PTE list. The contents of the field is a quadword index off the base of page table space. Free system PTEs and free global PTEs are linked together in this manner.

PTE$M_SINGLE_SPTE PTE$M_SINGLE_PTE A mask or flag denoting whether a free element describes a single PTE or multiple PTEs.

PTE$V_SINGLE_SPTE None The contents of a free PTE element are AND'ed with PTE$M_SINGLE_PTE to determine whether the element describes a single PTE.

**Table 3-1 Removed Date Structure Fields**
Removed Field	Replacement	Comments
BOD$L_BASEPVA	BOD$PQ_BASEPVA	64-bit process virtual address of buffer mapped by the buffer object. See Appendix A.
CDRP$L_AST	cdrp$pq_acb64_ast	Increased to a quadword and renamed.
CDRP$L_ASTPRM	CDRP$Q_A	See Appendix A.
CDRP$L_IOSB	CDRP$PQ_IOSB	See Appendix A.
CPT$L_IOVA	CPT$PQ_IOVA	Increased to a quadword and renamed.
DMP$M_BITS_12_15	Still have this field.	Same value.
DMP$S_BITS_12_15	Still have this field.	Same value.
DMP$V_BITS_12_15	Still have this field.	Same value.
DYN$C_F64_F64DATA	TBS---Dollar
DYN$C_NET_TIM_TEB	DYN$C_NET_TIM_NTEB	Renamed because the DECnet structure it indicates (network timer element block) was renamed from TEB to NTEB.
FDT_CONTEXT$L_QIO_R1_VALUE	FDT_CONTEXT$Q_QIO_R1_VALUE	See Appendix A.
IRP$L_AST	IRP$PQ_ACB64_AST	Removed to ensure that any reference to the $QIO astadr via a 32-bit address and astprm as a 32-bit value are detected at compile-time or link-time.
IRP$L_ASTPRM	IRP$Q_ACB64_ASTPRM	Removed to ensure that any reference to the $QIO astadr via a 32-bit address and astprm as a 32-bit value are detected at compile-time or link-time.
IRP$L_IOSB	IRP$PQ_IOSB	Removed to ensure that any reference to the $QIO iosb via a 32-bit address is detected at compile-time or link-time.
IRPE$L_BCNT1	IRPE$L_BCNT	See Appendix A.
IRPE$L_BCNT2	None.	Removed.
IRPE$L_BOFF1	IRPE$L_BOFF	See Appendix A.
IRPE$L_BOFF2	None.	Removed.
IRPE$L_SVAPTE1	IRPE$L_SVAPTE
IRPE$L_SVAPTE2	None.	Removed.
LCKCTX$L_CPLADR	LCKCTX$PQ_CPLADR	Increased in length to quadword.
LCKCTX$L_CPLPRM	LCKCTX$Q_CPLPRM	Increased in length to quadword.
LCKCTX$L_CR3	LCKCTX$Q_CR3	Increased in length to quadword.
LCKCTX$L_CR4	LCKCTX$Q_CR4	Increased in length to quadword.
LCKCTX$L_CR5	LCKCTX$Q_CR5	Increased in length to quadword.
LCKCTX$L_CRETADR	LCKCTX$PQ_CREADR	Increased in length to quadword.
LCKCTX$L_CTX_PRM1	LCKCTX$Q_CTX_PRM1	Increased in length to quadword.
LCKCTX$L_CTX_PRM2	LCKCTX$Q_CTX_PRM2	Increased in length to quadword.
LCKCTX$L_CTX_PRM3	LCKCTX$Q_CTX_PRM3	Increased in length to quadword.
LCKCTX$L_RET1	LCKCTX$PQ_RET1	Increased in length to quadword.
LCKCTX$L_TMP1	LCKCTX$Q_TMP1	Increased in length to quadword.
LKB$C_ACBLEN	Removed.
LKB$K_ACBLEN	Removed.
LKB$L_AST	LKB$PQ_AST	Increased in length to quadword.
LKB$L_ASTPRM	LKB$Q_ASTPRM	Increased in length to quadword.
LKB$L_BLKASTADR	LKB$PQ_CPLASTADR	Increased in length to quadword.
LKB$L_CPLASTADR	LKB$PQ_CPLASTADR	Increased in length to quadword.
LKB$L_LKSB	LKB$PQ_LKSB	Increased in length to quadword.
LKB$L_OLDASTPRM	LKB$Q_OLDASTPRM	Increased in length to quadword.
LKB$L_OLDBLKAST	LKB$PQ_OLDBLKAST	Increased in length to quadword.
LMB$C_GBL	No name change.	Value changed from 2 to 3.
LMB$C_PROCESS	No name change.	Value changed from 3 to 4.
LMB$C_S0	LMB$C_S0S1	Value = 1
LMB$C_SPT	LMB$C_SPTW	Not guaranteed to be in a dump.
LMB$L_BAD_MEM_END	LMB$PQ_BAD_MEM_END	Supports a 64-bit address.
LMB$L_BAD_MEM_START	LMB$PQ_BAD_MEM_START	Supports a 64-bit address.
LMB$L_HOLE_START_VA	LMB$PQ_BAD_MEM_START	Supports a 64-bit address.
LMB$L_HOLE_TOTAL_PAGES	LMB$Q_HOLE_TOTAL_PAGES	Supports a 64-bit address.
MMG$C_PTSPACE_OFFSET MMG$K_PTSPACE_OFFSET	MMG$GL_L1_INDEX	Compile-time constant that defined a fixed base address for page table address space. This has been replaced by a run-time mechanism which chooses a base address for page table address space during bootstrap, with the index of level 1 page table entry used to map the page tables stored in the new data cell.
PCB$L_ADB_LINK	None	Supported a feature that was never implemented.
PCB$L_PSX_ACTPRM	PCB$Q_PSX_ACTPRM	Increased in length to quadword.
PCB$L_TOTAL_EVTAST	None	Supported a feature that was never implemented.
PFN$C_ENTRY_SHIFT_SIZE	None	The size of a single PFN database entry was formerly a power of two. As of Version 7.0, that is no longer true and the symbol was deleted.
PFN$L_PTE		This offset in the PFN database was replaced with a new PTE backpointer mechanism that is capable of supporting page table entries that reside in 64-bit virtual address space. Any code that formerly touched PFN$L_PTE must be recoded to use one of the following macros supplied in LIB.MLB: ACCESS_BACKPOINTER ESTABLISH_BACKPOINTER TEST_BACKPOINTER
	ACCESS_BACKPOINTER	Accepts a PFN database entry address and returns a virtual address at which you may access the PTE that maps that PFN. This replaces a fetch of a SVAPTE from PFN$L_PTE, which would subsequently be used as an operand for a memory read or write instruction.
	ESTABLISH_BACKPOINTER	Replaces a write of a SVAPTE to PFN$L_PTE.
	TEST_BACKPOINTER	Replaces a test for zero in PFN$L_PTE.
PFN$L_REFCNT	INCREF DECREF	This offset in the PFN database was replaced with a differently sized offset that is packed together with other fields in the PFN database. The supplied macro INCREF should be used to replace any existing increment of the value in PFN$L_REFCNT, while DECREF should be used to replace any existing decrement.
PFN$L_WSLX	PFN$L_WSLX_QW	This offset was renamed to reflect a fundamental change in working set list indexes. Prior to Version 7.0, the working set list index (WSLX) was a longword index. The WSLX has become a quadword index as of Version 7.0, therefore the name of the offset was changed to focus attention on existing code that must be changed to view the value stored at this offset as a quadword index rather than as a longword index.
PHD$C_PHDPAGCTX	None	Supported a feature that was never implemented.
PHD$L_BAK	PHD$L_BAK_ARRAY	PHD$L_BAK contained an offset to an internally maintained array which was used to support swapping of the balance slot contents. As of Version 7.0, the implementation of this array changed to better accommodate the balance slot contents. PHD$L_BAK was replaced by PHD$L_BAK_ARRRAY which is the symbolic offset from the start of the process header to where this array begins.
PHD$L_L2PT_VA	L2PTE_VA	This process header offset formerly contained the system space address of the process's level 2 page table page that was used to map P0 and P1 spaces. As of Version 7.0, the page tables no longer reside in the balance slot, and a process is no longer limited to having only one level 2 page table page. This offset was used to derive addresses of level 2 page table entries. Use the L2PTE_VA macro to derive from a given VA the address of the level 2 PTE that maps that VA.
PHD$L_L3PT_VA PHD$L_L3PT_VA_P1	PTE_VA	These process header offsets formerly contained the system space addresses of the bases of the P0 and P1 page tables that resided in the process's balance slot. As of Version 7.0, the page tables no longer reside in the balance slot, and the conceptual overlap of the P0 and P1 page tables in virtual memory no longer exists. Use the PTE_VA macro to derive from a given VA the address of the level 3 PTE that maps that VA.
PHD$L_P0LENGTH	None	Different page table layout.
PHD$L_P1LENGTH	None	Different page table layout.
PHD$L_PSTBASMAX	PHD$L_PST_BASE_MAX	Contains new-style section index.
PHD$L_PSTBASOFF	PHD$L_PST_BASE_OFFSET	Name changed.
PHD$L_PSTFREE	PHD$L_PST_FREE	Contains new-style section index.
PHD$L_PSTLAST	PHD$L_PST_LAST	Contains new-style section index.
PHD$L_PTWSLELCK PHD$L_PTWSLEVAL	PFN database	These process header offsets formerly contained internal bookkeeping information for managing page table pages for a process. These have been replaced by a bookkeeping mechanism that resides in the PFN database entries for page table pages. It is highly unlikely that anyone is affected by this change.
PHD$L_QUANT	KTB$L_QUANT
PHD$L_WSL	CTL$GQ_WSL	You can no longer count on WSL (data cell) following PHD, use pointer to WSL in CTL$GQ_WSL instead.
PHD$L_WSLX	None	WSLX array is no longer in PHD as a result of the new swapper design.
PTE$L_COUNT	PTE$L_FREE_COUNT	Offset to the number of free PTEs in a free PTE structure.
PTE$L_LINK	PTE$Q_INDEX	Contains an index to the next free element in the free PTE list. The contents of the field is a quadword index off the base of page table space. Free system PTEs and free global PTEs are linked together in this manner.
PTE$M_SINGLE_SPTE	PTE$M_SINGLE_PTE	A mask or flag denoting whether a free element describes a single PTE or multiple PTEs.
PTE$V_SINGLE_SPTE	None	The contents of a free PTE element are AND'ed with PTE$M_SINGLE_PTE to determine whether the element describes a single PTE.

3.2 Removed Routines

Table 3-2 lists the routines that have been removed as of OpenVMS Alpha Version 7.0.

Table 3-2 Removed Routines
Removed Routine Replacement Comments

MMG$ALCSTX MMG_STD$ALCSTX Returns new-style section index.

MMG$ALLOC_PFN_ALGND MMG$ALLOC_PFN_ALGND_64 MMG$ALLOC_PFN_ALGND_64 should not be called directly. Instead, use the ALLOCPFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.

MMG$ALLOC_ZERO_ALGND MMG$ALLOC_ZERO_ALGND_64 MMG$ALLOC_ZERO_ALGND_64 should not be called directly. Instead, use the ALLOC_ZERO_PFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.

MMG$CREPAG MMG$CREPAG_64
MMG_STD$CREPAG_64 Accepts 64-bit addresses and has 3 new inputs: RDE (R12), pagefile_cache (R13) mmg_flags (R14). See mmg_routines.h for STD interface.

MMG$DALCSTX MMG_STD$DALCSTX Accepts new-style section index.

MMG$DECPTREF MMG_STD$DECPTREF_PFNDB
MMG_STD$DECPTREF_GPT MMG$DECPTREF expected a 32-bit system space address of a PTE as an input parameter. Page table entries are now located in 64-bit addressable memory. This routine was replaced by two routines: MMG_STD$DECPTREF_PFNDB and MMG_STD$DECPTREF_GPT.
MMG_STD$DECPTREF_PFNDB accepts as input a 64-bit virtual address of a PFN database entry for a page table, the reference count of which is to be decremented.
MMG_STD$DECPTREF_GPT, accepts as input a 64-bit virtual address of a global page table entry, which lies within a certain global page table page, of which a reference count must be decremented.

MMG$DECSECREF MMG_STD$DECSECREF Accepts new-style section index.

MMG$DECSECREFL MMG_STD$DECSECREFL Accepts new-style section index.

MMG$DELPAG MMG$DELPAG_64
MMG_STD$DELPAG_64 Accepts 64-bit addresses and has 2 new inputs, RDE (R12) and mmg_flags (R14). See mmg_routines.h for STD interface.

MMG$DELWSLEPPG MMG_STD$DELWSLEPPG_64 Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.

MMG$DELWSLEX MMG_STD$DELWSLEX_64 Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.

MMG$FREWSLX MMG$FREWSLX_64 Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.

MMG$GETGSNAM MMG_STD$GETGSNAM Converted to STD interface. (No prototype in mmg_routines.h.)

MMG$GSDSCAN MMG_STD$GSDSCAN Converted to STD interface. See mmg_routines.h for interface definition.

MMG$INCPTREF MMG_STD$INCPTREF_64 Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.

MMG$INIBLDPKT None This routine was used internally only. Its symbol has been removed from the base image.

MMG$ININEW_PFN MMG_STD$ININEWPFN_64 Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.

MMG$INIT_PGFLQUOTA MMG_STD$INIT_PGFLQUOTA
$INIT_PGFLQUOTA Converted to STD interface. See mmg_functions.h for interface definition.

MMG$IN_REGION MMG_STD$IN_REGION_64
$IN_REGION_64 Converted to STD interface. See mmg_functions.h for interface definition.

MMG$IOLOCK MMG_STD$IOLOCK_BUF See Appendix B.

MMG$LOCKPGTB MMG_STD$LOCKPGTB_64 Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.

MMG$MAKE_WSLE MMG_STD$MAKE_WSLE_64 Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.

MMG$MORE_PGFLQUOTA MMG_STD$MORE_PGFLQUOTA
$MORE_PGFLQUOTA Converted to STD interface. See mmg_functions.h for interface definition.

MMG$MOVPTLOCK
MMG$MOVPTLOCK1 None Page table locking redesign has obviated these routines. No replacement exists.

MMG$PTEINDX None Used internally only. Obviated by design as of Version 7.0.

MMG$PTEREF MMG$PTEREF_64 This replacement reflects a change in interface including MMG_STD$PTEREF acceptance as input a 64-bit virtual address.

MMG$PURGEMPL MMG$PURGE_MPL Renamed because the interface changed slightly. This is a JSB entry with arguments in R0-R2. It now accepts an additional argument in R3, the PTBR of the process owning the PTEs, for range-based requests. This request type also now accepts 64-bit PTE addresses rather than 32-bit SVAPTE addresses.

MMG$SUBSECREF MMG_STD$DECSECREFL Accepts new-style section index.

MMG$SUBSECREFL MMG_STD$SUBSECREFL Accepts new-style section index.

MMG$TBI_SINGLE_64 TBI_SINGLE Macro MMG$TBI_SINGLE_64 should not be called directly. Instead, use the TBI_SINGLE macro.

MMG$TRY_ALL MMG_STD$TRY_ALL_64 Converted to STD interface. See mmg_routines.h for interface definition.

MMG$ULKGBLWSL None This routine was used internally only. Its symbol has been removed from the base image.

MMG$UNLOCK MMG_STD$IOUNLOCK_BUF See Appendix B.

MMG_STD$ALLOC_PFN MMG_STD$ALLOC_PFN_64 This routine should not be called directly. Instead, use the ALLOCPFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$ALLOC_ZERO_PFN MMG_STD$ALLOC_ZERO_PFN_64 This routine should not be called directly. Instead, use the ALLOC_ZERO_PFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$DALLOC_PFN MMG_STD$DALLOC_PFN_64 Note that 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$DEL_PFNLST MMG_STD$DEL_PFNLST_64 Note that 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$ININEW_PFN MMG_STD$ININEWPFN_64 Note that 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$INS_PFNH MMG_STD$INS_PFNH_64 Note that the 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$INS_PFNT MMG_STD$INS_PFNT_64 Note that the 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$IOLOCK MMG_STD$IOLOCK_BUF See Appendix B.

MMG_STD$PTEINDX None Used internally only. Obviated by design as of OpenVMS Alpha Version 7.0.

MMG_STD$REL_PFN MMG_STD$REL_PFN_64 Note that the 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$REM_PFN MMG_STD$REM_PFN_64 Note that the 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$REM_PFNH MMG_STD$REM_PFNH_64 Note that the 64-bit virtual addresses are required to access PFN database entries.

MMG_STD$TBI_SINGLE_64 TBI_SINGLE Macro MMG_STD$TBI_SINGLE_64 should not be called directly. Instead, use the TBI_SINGLE macro.

MMG_STD$UNLOCK MMG_STD$IOUNLOCK_BUF See Appendix B.

SWP$FILL_L1L2_PT None Removed.

**Table 3-2 Removed Routines**
Removed Routine	Replacement	Comments
MMG$ALCSTX	MMG_STD$ALCSTX	Returns new-style section index.
MMG$ALLOC_PFN_ALGND	MMG$ALLOC_PFN_ALGND_64	MMG$ALLOC_PFN_ALGND_64 should not be called directly. Instead, use the ALLOCPFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.
MMG$ALLOC_ZERO_ALGND	MMG$ALLOC_ZERO_ALGND_64	MMG$ALLOC_ZERO_ALGND_64 should not be called directly. Instead, use the ALLOC_ZERO_PFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.
MMG$CREPAG	MMG$CREPAG_64 MMG_STD$CREPAG_64	Accepts 64-bit addresses and has 3 new inputs: RDE (R12), pagefile_cache (R13) mmg_flags (R14). See mmg_routines.h for STD interface.
MMG$DALCSTX	MMG_STD$DALCSTX	Accepts new-style section index.
MMG$DECPTREF	MMG_STD$DECPTREF_PFNDB MMG_STD$DECPTREF_GPT	MMG$DECPTREF expected a 32-bit system space address of a PTE as an input parameter. Page table entries are now located in 64-bit addressable memory. This routine was replaced by two routines: MMG_STD$DECPTREF_PFNDB and MMG_STD$DECPTREF_GPT. MMG_STD$DECPTREF_PFNDB accepts as input a 64-bit virtual address of a PFN database entry for a page table, the reference count of which is to be decremented. MMG_STD$DECPTREF_GPT, accepts as input a 64-bit virtual address of a global page table entry, which lies within a certain global page table page, of which a reference count must be decremented.
MMG$DECSECREF	MMG_STD$DECSECREF	Accepts new-style section index.
MMG$DECSECREFL	MMG_STD$DECSECREFL	Accepts new-style section index.
MMG$DELPAG	MMG$DELPAG_64 MMG_STD$DELPAG_64	Accepts 64-bit addresses and has 2 new inputs, RDE (R12) and mmg_flags (R14). See mmg_routines.h for STD interface.
MMG$DELWSLEPPG	MMG_STD$DELWSLEPPG_64	Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.
MMG$DELWSLEX	MMG_STD$DELWSLEX_64	Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.
MMG$FREWSLX	MMG$FREWSLX_64	Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.
MMG$GETGSNAM	MMG_STD$GETGSNAM	Converted to STD interface. (No prototype in mmg_routines.h.)
MMG$GSDSCAN	MMG_STD$GSDSCAN	Converted to STD interface. See mmg_routines.h for interface definition.
MMG$INCPTREF	MMG_STD$INCPTREF_64	Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.
MMG$INIBLDPKT	None	This routine was used internally only. Its symbol has been removed from the base image.
MMG$ININEW_PFN	MMG_STD$ININEWPFN_64	Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.
MMG$INIT_PGFLQUOTA	MMG_STD$INIT_PGFLQUOTA $INIT_PGFLQUOTA	Converted to STD interface. See mmg_functions.h for interface definition.
MMG$IN_REGION	MMG_STD$IN_REGION_64 $IN_REGION_64	Converted to STD interface. See mmg_functions.h for interface definition.
MMG$IOLOCK	MMG_STD$IOLOCK_BUF	See Appendix B.
MMG$LOCKPGTB	MMG_STD$LOCKPGTB_64	Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.
MMG$MAKE_WSLE	MMG_STD$MAKE_WSLE_64	Replacement reflects a change in input from a 32-bit addressable system space address of a PTE to a 64-bit address of a PTE in page table space. Other argument changes may have occurred as well.
MMG$MORE_PGFLQUOTA	MMG_STD$MORE_PGFLQUOTA $MORE_PGFLQUOTA	Converted to STD interface. See mmg_functions.h for interface definition.
MMG$MOVPTLOCK MMG$MOVPTLOCK1	None	Page table locking redesign has obviated these routines. No replacement exists.
MMG$PTEINDX	None	Used internally only. Obviated by design as of Version 7.0.
MMG$PTEREF	MMG$PTEREF_64	This replacement reflects a change in interface including MMG_STD$PTEREF acceptance as input a 64-bit virtual address.
MMG$PURGEMPL	MMG$PURGE_MPL	Renamed because the interface changed slightly. This is a JSB entry with arguments in R0-R2. It now accepts an additional argument in R3, the PTBR of the process owning the PTEs, for range-based requests. This request type also now accepts 64-bit PTE addresses rather than 32-bit SVAPTE addresses.
MMG$SUBSECREF	MMG_STD$DECSECREFL	Accepts new-style section index.
MMG$SUBSECREFL	MMG_STD$SUBSECREFL	Accepts new-style section index.
MMG$TBI_SINGLE_64	TBI_SINGLE Macro	MMG$TBI_SINGLE_64 should not be called directly. Instead, use the TBI_SINGLE macro.
MMG$TRY_ALL	MMG_STD$TRY_ALL_64	Converted to STD interface. See mmg_routines.h for interface definition.
MMG$ULKGBLWSL	None	This routine was used internally only. Its symbol has been removed from the base image.
MMG$UNLOCK	MMG_STD$IOUNLOCK_BUF	See Appendix B.
MMG_STD$ALLOC_PFN	MMG_STD$ALLOC_PFN_64	This routine should not be called directly. Instead, use the ALLOCPFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$ALLOC_ZERO_PFN	MMG_STD$ALLOC_ZERO_PFN_64	This routine should not be called directly. Instead, use the ALLOC_ZERO_PFN macro. Note that 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$DALLOC_PFN	MMG_STD$DALLOC_PFN_64	Note that 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$DEL_PFNLST	MMG_STD$DEL_PFNLST_64	Note that 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$ININEW_PFN	MMG_STD$ININEWPFN_64	Note that 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$INS_PFNH	MMG_STD$INS_PFNH_64	Note that the 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$INS_PFNT	MMG_STD$INS_PFNT_64	Note that the 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$IOLOCK	MMG_STD$IOLOCK_BUF	See Appendix B.
MMG_STD$PTEINDX	None	Used internally only. Obviated by design as of OpenVMS Alpha Version 7.0.
MMG_STD$REL_PFN	MMG_STD$REL_PFN_64	Note that the 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$REM_PFN	MMG_STD$REM_PFN_64	Note that the 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$REM_PFNH	MMG_STD$REM_PFNH_64	Note that the 64-bit virtual addresses are required to access PFN database entries.
MMG_STD$TBI_SINGLE_64	TBI_SINGLE Macro	MMG_STD$TBI_SINGLE_64 should not be called directly. Instead, use the TBI_SINGLE macro.
MMG_STD$UNLOCK	MMG_STD$IOUNLOCK_BUF	See Appendix B.
SWP$FILL_L1L2_PT	None	Removed.

3.3 Removed Macros

This section lists the macros that have been removed as of OpenVMS Alpha Version 7.0.

3.3.1 Removed MACRO-32 Macros Formerly in SYS$LIBRARY:LIB.MLB

$VADEF --- Moved to SYS$LIBRARY:STARLET.MLB
TBI_SINGLE_64 --- MMG$TBI_SINGLE_64

3.3.2 C Header Files Removed From SYS$LIBRARY:SYS$LIB_C.TLB

msb_codec_reg.h
msb_reg.h
vadef.h --- Moved to SYS$LIBRARY:SYS$STARLET_C.TLB

  6466P002.HTM
  OSSG Documentation
  22-NOV-1996 13:11:31.97

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