Migrating an Application from OpenVMS VAX to OpenVMS Alpha

Read-modify-write operations are typically not atomic at an instruction level on a RISC machine.

byte granularity: A property of memory systems in which adjacent bytes can be written concurrently and independently by different processes or processors.

CISC: See complex instruction set computer.

compatibility: The ability of programs written for one type of computer system (such as OpenVMS VAX) to execute on another type of system (such as OpenVMS Alpha).

complex instruction set computer (CISC): A computer that has individual instructions that perform complex operations, including complex operations performed directly on locations in memory. Examples of such operations include instructions that do multibyte data moves or substring searches. CISC computers are typically contrasted with RISC (reduced instruction set computer) computers.

concurrency: Simultaneous operations by multiple agents on a shared object.

cross development: The process of creating software using tools running on one system, but targeted for another type of system; for example, creating code for Alpha systems using tools running on a VAX system.

granularity: A characteristic of storage systems that defines the amount of data that can be read or written with a single instruction, or read or written independently. VAX systems have byte or multibyte granularities while disk systems typically have 512-byte or greater granularities.

image information file (IIF): An ASCII file that contains information about the interface between VAX images. VEST uses IIFs to resolve references to other images and to generate the appropriate linkages.

image section: A group of program sections with the same attributes (such as read-only access, read/write access, absolute, relocatable, and so on) that is the unit of virtual memory allocation for an image.

interlocked instruction: An instruction that performs some action in a way that guarantees the complete result as a single, uninterruptible operation in a multiprocessing environment. Since other potentially conflicting operations can be blocked while the interlocked instruction completes, interlocked instructions can have a negative performance impact.

jacket routine: A procedure that converts procedure calls from one calling standard to another; for example, calls between translated VAX images, which use the VAX calling standard, and native Alpha images, which use the Alpha calling standard.

load/store architecture: A machine architecture in which data items are first loaded into a processor register, then operated on, and finally stored back to memory. No operations on memory other than load and store are provided by the instruction set.

longword: Four contiguous bytes (32 bits) starting on any addressable byte boundary. Bits are numbered from right to left, 0 to 31. The address of the longword is the address of the byte containing the low-order bit (bit 0). A longword is naturally aligned if its address is evenly divisible by 4.

multiple instruction issue: Issuing more than one instruction during a single clock cycle.

natural alignment: Data storage in memory such that the address of the data is evenly divisible by the size of the data in bytes. For example, a naturally aligned longword has an address that is evenly divisible by 4, and a naturally aligned quadword has an address that is evenly divisible by 8. A structure is naturally aligned when all its members are naturally aligned.

page size: The number of bytes that a system's hardware treats as a unit for address mapping, sharing, protection, and movement to and from secondary storage.

pagelet: A 512-byte unit of memory in an Alpha environment. On Alpha systems, certain DCL and utility commands, system services, and system routines accept as input or provide as output memory requirements and quotas in terms of pagelets. Although this allows the external interfaces of these components to be compatible with those of VAX systems, OpenVMS Alpha internally manages memory only in even multiples of the CPU memory page size.

PALcode: See privileged architecture library.

privileged architecture library (PAL): A library of callable routines for performing instructions unique to a particular operating system. Special instructions call the routines, which must run without interruption.

processor status (PS): On Alpha systems, a privileged processor register consisting of a quadword of information including the current access mode, the current interrupt priority level (IPL), the stack alignment, and several reserved fields.

processor status longword (PSL): On VAX systems, a privileged processor register consisting of a word of privileged processor status and the processor status word itself. The privileged processor status information includes the current interrupt priority level (IPL), the previous access mode, the current access mode, the interrupt stack bit, the trace trap pending bit, and the compatibility mode bit.

processor status word (PSW): On VAX systems, the low-order word of the processor status longword. Processor status information includes the condition codes (carry, overflow, 0, negative), the arithmetic trap enable bits (integer overflow, decimal overflow, floating underflow), and the trace enable bit.

program counter (PC): That portion of the CPU that contains the virtual address of the next instruction to be executed. Most current CPUs implement the program counter as a register. This register is visible to the programmer through the instruction set.

quadword: Four contiguous words (64 bits) starting on any addressable byte boundary. Bits are numbered from right to left, 0 to 63. The address of a quadword is the address of the word containing the low-order bit (bit 0). A quadword is naturally aligned if its address is evenly divisible by 8.

quadword granularity: A property of memory systems in which adjacent quadwords can be written concurrently and independently by different processes or processors.

read-modify-write operation: A hardware operation that involves the reading, modifying, and writing of a piece of data in main memory as a single, uninterruptible operation.

read-write ordering: The order in which memory on one CPU becomes visible to an execution agent (a different CPU or device within a tightly coupled system).

reduced instruction set computer (RISC): A computer that has an instruction set reduced in complexity, but not necessarily in the number of instructions. RISC architectures typically require more instructions than CISC architectures to perform a given operation, because an individual instruction performs less work than a CISC instruction.

RISC: See reduced instruction set computer.

synchronization: A method of controlling access to some shared resource so that predictable, well-defined results are obtained when operating in a multiprocessing environment or in a uniprocessing environment using shared data.

translated code: The native Alpha object code in a translated image. Translated code includes:

Alpha code that reproduces the behavior of equivalent VAX code in the original image
Calls to the Translated Image Environment (TIE)

translated image: An Alpha executable or shareable image created by translation of the object code of a VAX image. The translated image, which is functionally equivalent to the VAX image from which it was translated, includes both translated code and the original image. See VAX Environment Software Translator.

Translated Image Environment (TIE): A native Alpha shareable image that supports the execution of translated images. The TIE processes all interactions with the native Alpha system and provides an environment similar to OpenVMS VAX for the translated image by managing VAX state; by emulating VAX features such as exception processing, AST delivery, and complex VAX instructions; and by interpreting untranslated VAX instructions.

translation: The process of converting a VAX binary image to an Alpha image that runs with the assistance of the TIE on an Alpha system. Translation is a static process that converts as much VAX code as possible to native Alpha instructions. The TIE interprets any untranslated VAX code at run time.

VEST: See VAX Environment Software Translator.

VAX Environment Software Translator (VEST): A software migration tool that performs the translation of VAX executable and shareable images into translated images that run on Alpha systems. See translated image.

word granularity: A property of memory systems in which adjacent words can be written concurrently and independently by different processes or processors.

writable global section: A data structure (for example, FORTRAN global common) or shareable image section potentially available to all processes in the system for use in communicating between processes.

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  OSSG Documentation
  22-NOV-1996 13:07:29.38

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